Reducing Glitching and Leakage Power in Low Voltage Cmos Circuits

The need for low power dissipation in portable computing and wireless communication is making design communities accept ultra low voltage CMOS processes. With the lowering of' supply voltage, the transistor thresholds (Vth) have to be scaled down to meet the performance requirements. However, such scaling can increase the leakage current through a transistor, thereby increasing the leakage power. It can also be noted that in static CMOS circuits, the paths converging t o any internal gate may have different propagation delays. The delay mismatch of' different paths causes spurious transitions. Such transitions increase the power dissipation due to the switching component of current. In this paper we present a novel algorithm to balance different paths of a design converging t o logic gates using multiple threshold transistors such that both p,ower dissipation due to spurious transitions and leakage current are minimized. Leakage power is reduced due t o the use of high threshold transistors in the non-critical paths. Results for ISCAS benchmark circuits show tha t the glitching power can be minimized by more than 30% using three different threshold voltages. The practicality of multiple threshold designs using dual-gated SO1 (Silicon-On-Insulator) technology is also discussed.